There has been known a wiring substrate on which a semiconductor chip can be mounted (see, for example, Patent Documents 1 and 2). Such a wiring substrate has connection terminals connectable to a semiconductor chip.
Patent Document 1 discloses a technique for preventing plating material from forming an electrical short circuit between connection terminals. According to the technique, an insulating layer having an opening for exposing a plurality of connection terminals is formed, insulation is formed between the connection terminals in the opening, and the connection terminals are plated. Patent Document 2 discloses a technique of thinning an insulating layer formed between connection terminals to a thickness equal to or smaller than the thickness of the connection terminals to thereby prevent solder from forming an electrical short circuit between the connection terminals.
When a semiconductor chip is mounted on a wiring substrate, the connection terminals of the wiring substrate are soldered to the semiconductor chip, and a liquid hardening resin called “underfill” is filled into a gap between the wiring substrate and the semiconductor chip around the connection terminals (see, for example, Patent Document 3).